Esterel Technologies>About us>Academic Education Program>Member Kit
Member of our Academic Education Program?
In return for free access to our software and training material, and as indicated in the academic contract, we require that you acknowledge this membership on your website, in the form of an academic badge, which consists of images plus text. All are compulsory and must not be modified. This will help our websites to be properly referenced. Please, follow the instructions and contact us if you have any questions. Thank you in advance.
Instructions to display the academic member badge
- Copy the HTML code available below on a page of your university website, COMPLETELY and with NO MODIFICATION
- When done, please send the corresponding web link to scade.education@esterel-technologies.com
HTML source code to copy&paste:
<p style="text-align:left;text-indent:0;width:384px;height:90px;margin-left:141px;font:13px/140% Verdana,sans-serif;color:black;position:relative;"><a href="http://www.esterel-technologies.com/technology/academic-program/members" title="Official Esterel Technologies Academic Partner">
<img style="border:none;position:absolute;left:-141px;display:block;" src="http://www.esterel-technologies.com/styles/img/badges/academic-member-128.png"alt="Official Esterel Technologies Academic Partner"/></a>
Academic partner of <a href="http://www.esterel-technologies.com/" style="font:13px/140% Verdana,sans-serif;color:#ff660f;" title="Esterel Technologies, the provider of model-based solutions for DO-178B and IEC 61508 safety-critical systems and control-intensive IPs">Esterel Technologies</a>, the provider of model-based solutions for
<a href="http://www.esterel-technologies.com/products/scade-suite/do-178b-code-generation" style="font:13px/140% Verdana,sans-serif;color:#ff660f;" title="DO-178B - Code Generator">DO-178B</a> and <a href="http://www.esterel-technologies.com/products/scade-drive/iec-61508-code-generation" title="IEC 61508 - Code Generator" style="font:13px/140% Verdana,sans-serif;color:#ff660f;">IEC 61508</a> <a href="http://www.esterel-technologies.com/services/software-design-verification/software-design-verification" title="Safety-critical" style="font:13px/140% Verdana,sans-serif;color:#ff660f;">safety-critical</a> systems.
</p>
<p style="text-align:left;text-indent:0;width:384px;height:90px;margin-left:141px;font:13px/140% Verdana,sans-serif;color:black;position:relative;"><a href="http://www.esterel-eda.com/corporate/academic-program/members.html" title="Official Esterel EDA Technologies Academic Partner">
<img style="border:none;position:absolute;left:-141px;display:block;" src="http://www.esterel-technologies.com/styles/img/badges/academic-member-esterel-eda-128.png"alt="Official Esterel EDA Technologies Academic Partner"/></a>
Academic partner of <a href="http://www.esterel-eda.com/" style="font:13px/140% Verdana,sans-serif;color:#ff660f;" title="Esterel EDA Technologies">Esterel EDA Technologies</a>
provider of <a href="http://www.esterel-eda.com/products/esl-synthesis-with-esterel-studio.html" style="font:13px/140% Verdana,sans-serif;color:#ff660f;" title="ESL synthesis"> ESL synthesis</a>
for <a href="http://www.esterel-eda.com/products/ip-design-applications.html" style="font:13px/140% Verdana,sans-serif;color:#ff660f;" title="control-intensive IP"> control-intensive IP</a> design and verification,
including <a href="http://www.esterel-eda.com/products/systemc-code-generator.html" style="font:13px/140% Verdana,sans-serif;color:#ff660f;" title="SystemC code generator">SystemC</a>,
<a href="http://www.esterel-eda.com/products/rtl-code-generator.html" style="font:13px/140% Verdana,sans-serif;color:#ff660f;" title="RTL code generator">VHDL, and Verilog</a> code generation
</p>
The academic badge will appear like this
Academic partner of Esterel Technologies, the provider of model-based solutions for
DO-178B and IEC 61508 safety-critical systems.
Academic partner of Esterel EDA Technologies
provider of ESL synthesis
for control-intensive IP design and verification,
including SystemC,
VHDL, and Verilog code generation
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