SCADE Suite Timing and Stack Verifiers
SCADE Suite Timing Verifier automatically verifies timing requirements for the SCADE Suite generated code on a specified processor target. It estimates Worst Case Execution Time (WCET) and reports the results at model level within SCADE Suite.
Computation of WCET and stack usage of a SCADE Suite application for a specific target
Aggregation of results from different code generation settings and comparison at model level
Fully automated process
Fully customizable from SCADE Suite or by Tcl scripts
Supported processor targets for WCET analysis: PowerPC e200 family, PowerPC MPC 5xx family, PowerPC e300, PowerPC MPC 755s, and ARM Cortex.
Supported processor targets for stack analysis: all PowerPC and ARM Cortex-R4
Available on request: LEON2, LEON3, NEC V850E1/PHO3, TriCores 1766/1796/1797