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SCADE Suite Timing and Stack Verifiers™

SCADE Suite 6.1 introduces new tools and features that enable the analysis of worst-case execution time (WCET) and stack usage on SCADE Suite models.

Timing and Stack Verifiers allow the designer to:

• Rapidly determine worst-case execution times and stack usage at model level.
• Examine how different functions of the SCADE Suite model contribute to the average, maximum, and cumulated execution times and stack usage.
• Optimize the design of the SCADE Suite model and thus improve the performance of the SCADE Suite application.
• Save considerable development time, cut development costs, and shorten time to market.

Timing and Stack Verifiers in the development process

Timing and Stack analysis tools

Fully understanding the worst-case execution time (WCET) and the stack usage of programs is crucial for the design of hard real-time systems; thus, timing and stack analysis have become an acknowledged and an essential part in the design of real-time systems.

SCADE Suite integrates Timing and Stack Verifiers to provide information on WCET and stack size of a SCADE Suite application and its sub-functions. By analysis of the binary code generated from the compiled SCADE Suite model and detailed target processor information, hierarchical resource usage data is calculated and displayed. Based on this information, designers can compare and optimize the design of their SCADE Suite models.

In addition to performing and displaying analysis on a single SCADE Suite model, the SCADE Suite Timing and Stack Verifiers allow the aggregating of multiple analysis session results to enable the designer to quantify the benefits of alternate design styles and code generation strategies.

Supported targets

• Supported processor targets for WCET analysis: MPC55xx, MPC555, MPC565, MPC603e, MPC755s.
• Supported processor targets for stack analysis: all PowerPC.