Esterel EDA>Customers>Usage and Benefits
What are the Benefits of Esterel Studio?
Faster development, better communication
- Most bugs are detected early at specification time rather than RTL coding and verification.
- Sharing a unique model for architecture, design and verification improves communication efficiency between teams.
- The automated RTL code generation ensures there are no differences between RTL and Esterel Studio executable specifications.
Better quality
- Formal verification of assertions stresses designs and provides efficient detection of complex bugs.
- There is 100% consistency between Esterel specification, SystemC simulation and RTL implementation.
- Area and speed performance of Esterel generated RTL is always same or better than that of manually coded RTL in all customer comparisons, ask us for details.
Cost reduction
- Automatic efficient synthesizable RTL generation saves coding time.
- Formal verification can reduce the number of bugs escaping to system-level simulation by up to 50%, which saves vast amount of bug corrections time.
- Esterel Studio shorter design cycle typically saves 30% overall project development time.
Who uses Esterel Studio?
Micro-architects
Micro-architects design executable specification and capture their micro-architecture with Esterel Studio. They distribute Executable Specifications together with paper documents as a reference shared with designers, verification engineers and remote teams, together with some design assertions the implementation should meet. The Executable Specification Player, available free of charge, enables remote teams to exercise executable specifications.
RTL Designers and Verification engineers
RTL Designers use Esterel Studio Executable specifications that they refine refine into design specification performing remaining optimizations, . They also check IP properties using the Design Verifier, generate RTL, connect to synthesis and back-end. Esterel Studio generated RTL is compliant with all synthesis and DFT tools. Esterel Studio IP can also smoothly go to accelerated verification platforms. Designers and Architects keep the Esterel Studio specification as a single always up-to-date reference.
System Architects
System architects use Esterel Studio generated SystemC to incorporate IP into their System Level exploration and virtual prototypes environment. System validation engineers also use Esterel Studio for specific tasks, incl. proofs of specific system properties, worst case dimensioning, chip-level validation. Smart card and security related application architects use Esterel Studio for systems specification and modelling.
