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Esterel Studio IP Design Targets

Todays' chips are so complex that new Electronic System Level (ESL) tools using higher level than RTL languages are called for. ESL tools rely on higher level languages than RTL that result in much faster and above all much saferIP design , since many low-level coding bugs are simpley avoided. Generating efficient RTL implementation from a high level ESL description is known as as ESL Synthesis. 

Esterel Studio is the leading front-end design and verification suite for control intensive IP. Esterel Studio delivers the full benefits of ESL Synthesis, providing an automated path from ESL to RTL by generating consistent VHDL/Verilog and SystemC from a single and formally verified IP executable specification.


Move your mouse over the graphic below to see detailed IP design targets by categories.

Processors

  • We do
    • Co-processor (e.g.Java hardware accelerator)
    • Multimedia data pre-processing
    • Deterministic sequencers
  • We don't
    • Standard cores (RISC, DSP)

Wireline

  • We do
    • Link Interface
    • ATM
    • Packet Processing Engines
    • 10/100/1000 Ethernet MAC
    • SPI (System Packet Interface)
    • Protocol Link Layers
  • We don't
    • Transceivers
    • Analog

Signal Processing and Mathematics

  • We do
    • Digital Filters
    • Correlators
    • Encryption
    • Error Correction, CRC
  • We don't
    • DSP Cores
    • Math Library
    • Modulation/Demodulation Library
    • Amplification

Peripheral Cores

  • We do
    • Peripheral Controllers
    • DMA
    • Memory Controllers, EMIF
    • Disk Controllers (serial ATA)
    • Instruction and Data Cache
    • GPIO
    • Real-time Clocks and Counters
    • Keyboard
  • We don't
    • Analog Voltage/Power control
    • Analog Transceivers
    • Hard-wired Switch Logic

Memory

  • We do
    • Memory Controllers
    • EMIF
    • Cache coherence
    • Co-simulation with Denali memory models
  • We don't
    • Memory Elements and arrays

Analog - Mixed Signal - Power management

  • We do
    • SoC Power Management
    • Battery Charge Interface
    • Power On Reset Control
  • We don't
    • ADC/DAC
    • Analog filters, comparators
    • Oscillator, PLL
    • Voltage regulation and reference
    • Operational amplifiers

Buses & Peripheral Interfaces

  • We do
    • Bus Arbiters, Bridges, Controllers
    • Master/Slave Interfaces
    • E.g. AMBA, AXI, PCI Express, SD/SDIO/SDMMC, USB, OCP, I2C, IEEE 1394, CAN
  • We don't
    • Analog PHYsical Access
    • Voltage Signalling (LVDS)

Wireless Communications

  • We do
    • Wireless and Multimedia Application Processors
    • Digital Baseband
    • Protocol Link Layers and MAC
    • GSM/GPRS/EDGE/UMTS, Wi-Fi, UWB
    • Send Receive state machines
    • E.g. OMAP, Nexperia, Nomadik, e-Gold
  • We don't
    • RF
    • Analog Transceivers
    • Baseband Analog Front End
    • Modem PHY/Analog
    • Power Amplifiers
    • DAC/ADC



We Do We Don't

Wireless Communications
  • - RF
  • - Analog Transceivers
  • - Baseband Analog Front End
  • - Modem PHY/Analog
  • - Power Amplifiers
  • - DAC/ADC

Processors
  • - Standard cores (RISC, DSP)

Peripheral Cores
  • - Peripheral Controllers
  • - DMA
  • - Memory Controllers, EMIF
  • - Disk Controllers (serial ATA)
  • - Instruction and Data Cache
  • - GPIO
  • - Real-Time Clocks and Counters
  • - Keyboard
  • - Analog Voltage/Power control
  • - Analog Transceivers
  • - Hard-wired Switch Logic

Buses & Peripheral Interfaces
  • - Analog PHYsical Access
  • - Voltage Signalling (LVDS)

Memory
  • Memory Elements and arrays

Wireline  Communications
  • - Link Interface
  • - ATM
  • - Packet Processing Engines
  • - 10/100/1000 Ethernet MAC
  • - SPI (System Packet Interface)
  • - Protocol Link Layers
  • - Transceivers
  • - Analog

Signal Processing and Mathematics
  • - Digital Filters
  • - Correlators
  • - Encryption
  • - Error Connection, CRC
  • - DSP Cores
  • - Math Library
  • - Modulation/Demodulation Library
  • - Amplification

Analog Mixed Signal Power Management
  • - ADC/DAC
  • - Analog filters, comparators
  • - Oscillator, PLL
  • - Voltage regulation and reference
  • - Operational amplifiers

Control-intensive IP designs are complex

  • correctness is critical and difficult to ensure, think about power and reset management
  • cycle allocation is part of the functional spec, that is a correct result one cycle too late is considered a bug
  • concurrent interacting state machines are difficult to analyze, which results in 4 times longer debugging than for data computation blocks

Esterel Studio is optimized for control-intensive IP Design


  • provides exact cycle control to the designer through powerful temporal control primitives
  • allows complex state machines description and powerful temporal control primitives to simplify design capture
  • includes a formal verification engine, only way to exhaustively verify concurrent state machines behavior

In contrast, ESL Synthesis tools designed for data-intensive designs provide different capabilities. Typically, different speed/area/latency tradeoffs are produced from a SystemC or C based description. As data-intensive designs essentially implement an algorithm, thay are perfectly described with SystemC or another algorithmic language. As it is functionally acceptable to delay or parallelize computations, such tools allocate computation cycles and propose various implementation micro-architectures. However, such tools are not well equipped to deal with the control-intensive designs requirements. 

Esterel Studio is often used together with other data-oriented ESL Synthesis tools. See ESL landscape and partners for an overview on this.



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