Esterel Technologies Releases Esterel Studio™ 5.4

Seamless and Interoperable ESL Synthesis

MOUNTAIN VIEW, California and ELANCOURT, France — December 19, 2006

Esterel Technologies today announced the release of the new version of Esterel Studio, the leading front-end design and verification suite for control-intensive hardware IP. Esterel Studio delivers the full benefits of ESL synthesis, providing an automated path from ESL to RTL by generating consistent VHDL/Verilog and SystemC implementations from a single and formally verified Esterel Studio IP executable specification. Esterel Studio includes an editor, a simulator, and supports assertions formal verification.

Esterel Studio 5.4 includes a completely revamped SystemC code generator that speeds up execution by a factor of five to ten. It also facilitates packaging and export of Esterel Studio executable specifications, and provides numerous formal verification enhancements.

The brand new SystemC code is optimized for execution speed needed for System-on-Chip design and prototyping. The new faster SystemC automatic code generation improves performance by factors between 5 and 10 depending on the design, a key factor to reduce system simulation times. Other C and C++ code generators have been upgraded accordingly.

An executable specifications exporter enables users to package a stand-alone simulator of their design, together with all necessary documentation and simulation scenarios. This simulator is ready for shipment to customers, remote teams, or suppliers. Recipients just need to download a free executable specifications player from Esterel Technologies website to instantly observe dynamic behavior of the specification.

In parallel to its RTL and SystemC outputs, Esterel Studio generates IP-XACT™ descriptions from The SPIRIT Consortium™, which ensures easy integration in multi-vendor flows. IP designers can now create and deliver parametric RTL IP to their customers, who then can tailor it to their needs using the Esterel Configurator.

The Design Verifier has been enhanced for improved usability, scalability, and integrates new functionality. Users can flexibly indicate IP blocks usage conditions, so that formal verification only detects genuine errors. Easy assertions selection, searching, sorting, archiving, and batch mode formal verification are all contributing to significantly improve productivity. The alternate use of assertions as verification goals and constraints provides a powerful divide-and-conquer strategy to manage verification complexity. An automatic sequential equivalence checker for secured optimizations completes the built-in formal verification tooling.

Our Esterel Studio 5.4 release will bring increased productivity to our customers’ design flows and the unique opportunity to obtain fast simulating SystemC prototypes and efficient hardware implementation from a single formal reference model of their IP, says Eric Bantegnie, Esterel Technologies’ CEO. In addition to developing new features, we also have completed our EDA partnerships to make sure Esterel Studio is connected to all ESL and RTL tools used by our customers, so they can be confident of smooth Esterel Studio deployment.

Esterel Studio 5.4 is available in LAN and WAN configurations, with one-year time-based licensing starting at $50,000 USD.

About Esterel Technologies

Esterel Technologies is the worldwide leader of model-based design and verification tools for critical embedded systems.

Esterel Studio™ is the market leading front-end design and verification suite for control-intensive hardware IP.

SCADE Suite™ is the market leading model-based development environment dedicated to safety-critical embedded software.

Esterel Technologies is a privately held company with headquarters in Elancourt, France and Mountain View, California, USA, and with direct sales offices in Germany, the United Kingdom, and China. For additional information, visit the Esterel Technologies website at www.esterel-technologies.com.

Esterel Technologies, Esterel Studio and SCADE are trademarks or registered trademarks of Esterel Technologies S.A. and Esterel Technologies, Inc. All other trademarks are the property of their respective owners.

Contact:

Jean-François Baggioni, Esterel Technologies

Phone : +33 (0)4 92 02 40 41

Email: eda@esterel-technologies.com

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