Esterel Technologies Releases Esterel Studio™ 5.3

Multiclock Esterel for power-optimized design

MOUNTAIN VIEW, California and ELANCOURT, France — January 19, 2006

Esterel Technologies today announced the release of Esterel Studio version 5.3, a comprehensive tool suite for the specification, design, and verification of complex IP blocks and hardware/software transactors. This version includes key features to design multiclock and power-optimized circuits and to generate SystemC from Esterel.

Esterel Studio version 5.3 adds new language statements to specify multiclocking and clock gating in a behavioral way, at the micro-architecture and functional levels. The new language primitives are independent of any implementation target. On ASICs, implementation is truly multiclock and uses clock gating. For FPGA emulation or software simulation, the identical design can be implemented, using clock disabling from a single base clock. The actual implementation depends solely on a compiling option. This avoids entirely the time-consuming and error-prone porting from an ASIC multiclock and clock-gated design to an FPGA-based virtual prototype, as well as the rewriting of an IP in C for software simulation. Within the short span of recompilation time, users can update an FPGA or software prototype to behaviorally reflect ASIC power management optimizations.

For software simulation, the Esterel to SystemC code generator has been upgraded to ensure that hardware/software transactors designed in Esterel seamlessly integrate in all software prototyping and hardware-accelerated environments. Transactors can be generated either in SystemC or in hardware with the same behavior. Esterel Studio is especially well suited to the type of transactor design typically needed when prototyping complex AMBA/AXI/PCI-based designs.

Version 5.3, which makes available all SystemC and multiclock RTL outputs, offers greater flexibility to choose the limit between the hardware and software within actual designs and virtual prototypes. Hardware transactors originally designed for simulation can be fully reused with the same source code for later ASIC implementation.

Including full multiclock and clock-gating support at all levels of the design flow in this release will further expand our applications into power-efficient and wireless designs, said Eric Bantegnie, CEO of Esterel Technologies. We have secured the performance of hardware IP and transactor design with Esterel and ensured interoperability with a dozen EDA tools, from system-level software environments, RTL simulation, and synthesis to DFT tools. We will now expand our C and SystemC capabilities.

Esterel Studio version 5.3 includes an editor, simulator, and formal verification capability. SystemC and C code generators enable connection to a system-level virtual prototyping environment. VHDL and Verilog code generators automatically turn an IP reference specification into a production-quality implementation. Version 5.3 also improves ergonomics and increases productivity through numerous enhancements concerning simulation, testbench handling, formal verification, sequential equivalence checking, automatic arithmetic assertion checks, and much more.

Esterel Studio 5.3 is available in LAN and WAN configurations, with one-year time-based licensing starting at U.S. $50,000

About Esterel Technologies

Esterel Technologies is a worldwide supplier of model-based design, validation, and code generation tools for safety-critical software and hardware applications. Esterel’s tools create unambiguous specifications that produce correct-by-construction, automated implementation of control designs in software and/or hardware. The product offering is based on two products: SCADE and Esterel Studio.

Esterel Technologies is a privately held company headquartered in Elancourt, France, and Mountain View, California. Esterel also has direct sales offices in Ottobrunn, Germany, Bracknell, United Kingdom, and Shanghai, P.R. China. Distributors in Japan, China, South Korea, Israel, and India complement the Esterel direct sales offices.

Contact:

Jean-François Baggioni, Esterel Technologies

Phone: +33 (0)4 92 02 40 41

Email: eda@esterel-technologies.com

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