Esterel Technologies

DATE 2007

April 16^th–20^th, 2007

Acropolis • Nice • France.

The only European Event for Electronic System Design & Test with over 100 companies showing the best in design, verification and test tools, platforms for embedded systems and electronic devices, IP cores and design services.

Be sure to stop on our booth : #R39.

Please attend our focus demonstrations

Formal Verification for the beginners with Esterel Studio built-in Design Verifier
Share unambiguous executable specifications with Esterel Studio free player™
Interoperable ESL synthesis flows for parametric IP design with IP-XACT™
Efficient ESL synthesis of control-intensive IP with Esterel Studio RTL code generator
Micro-architecture editor preview

	Tuesday, 17th April, 2007	Wednesday, 18th April, 2007	Thursday, 19th April, 2007
10.00	Share unambiguous executable specifications with Esterel Studio free player	Interoperable ESL synthesis flows for parametric IP design withIP-XACT	Share unambiguous executable specifications with Esterel Studio free player
11.00	Formal Verification for the beginners with Esterel Studio built-in Design Verifier	Efficient ESL synthesis of control-intensive IP with Esterel Studio RTL code generator	Formal Verification for the beginners with Esterel Studio built-in Design Verifier
14.00	Interoperable ESL synthesis flows for parametric IP design withIP-XACT	Share unambiguous executable specifications with Esterel Studio free player	Interoperable ESL synthesis flows for parametric IP design withIP-XACT
15.00	Micro-architecture editor preview browser navigator	Micro-architecture editor preview browser navigator	Micro-architecture editor preview browser navigator
16.00	Efficient ESL synthesis of control-intensive IP with Esterel Studio RTL code generator	Formal Verification for the beginners with Esterel Studio built-in Design Verifier	Efficient ESL synthesis of control-intensive IP with Esterel Studio RTL code generator

Registration

The demos have a duration of 15 Minutes, with a Q&A session following the presentation.

Demonstrations at other times can also be organized at your convenience.

Who should attend

The demonstrations are intended for architects, designers and verification engineers interested in IP and SoC design.