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Esterel Studio Customer Success Stories
All of the designs mentioned below are industrial designs realized by companies who are member of the Esterel Consortium. If your company is already a member, you have access to a restricted area which provides more projects details. We can also put you in contact with a customer who has Esterel Studio experience for the type of design you are considering.
Processor IP design, validation and synthesis
Full instruction processor, with datapath, ALUs, and complex distributed pipeline control. Completely synthesized with Magma BlastRTL, frequency target of more than 250 MHz reached. This design contains 30 Esterel blocks, 20 thousand lines of Esterel code. The full instruction processor was completely designed and validated by a mere team of 4 design and verification engineers fluent in Esterel. Formal verification used to verify pipeline control and detected bugs at depth 7 that could never have been detected manually, says the architect. Over 90 assertions described and proved using built-in Design Verifier.
Complex SoC Power Management
Power management is a key of modern mobile and wireless SoCs. Design of power managers is difficult because of their massively parallel control, and the complexity of power-related action sequences. A wireless customer defined and applies a new formal methodology for the specification and design of power managers. Key elementst of Esterel Studio enabling this methodology are: hierarchical concurrent state machines handling, executables specification dynamically exercised, formal verification to check temporal power mode properties and synchronization. Publications are expected soon.
Serial ATA disk controller link layer protocol specification and synthesis
Esterel source is 4 times smaller than HDL comparison design. Better synthesis area (5%), no routing congestion. A bug that went undetected for a long time in the original RTL design was avoided, because of Esterel specific control instructions like 'abort' which completely prevent this kind of bugs.
High throughput Direct Memory Access (DMA) for video processor
Design and synthesis of a highly configurable multi-channel DMA capable of sustaining very fast Direct Memory Access transfers. The DMA serves a video pipeline processor of very high throughput, since some algorithms require several hundreds of giga operations per seconds. The DMA serves complex requests to get video rectangles from various memory channels. It can pack and unpack various video formats on the fly, and process requests out of order while always sending results in order. A 4500 Esterel lines design, highly parametric, thanks to Esterel nice structured interfaces, ports and array processing.
Note: Esterel Studio has been successfuly applied to many customer DMA designs. In fact, DMA are often adapted to new SoC architectures and seldom reused as is. They must be completely reverified, and it is very tedious to do so, as the combination of concurrent channels, transfer modes, FIFO status etc. result in very large state spaces hardly verifyable without formal techniques. Esterel Studio DMAs are compact, readable, much easier to modify than RTL, and their verification can be largely automated.
Video IP specification to RTL and tests
The first multi-clock design achieved with Esterel Studio in 2004, completely verified and synthesized. Esterel synthesis performance showed 5% area gain over hand-coded RTL and same speed, for a customer qualified rather agressive timing constraint. An article published the methodlogy used.
Note: This consortium design served to develop the compllete multi-clock Esterel Studio, which now routinely automates design, simulation and verification of multi-clock designs since 2005.
FlashCard sub-system specification to FPGA prototype
This design is a SD/MMC multi-mode controller including complete virtual memory management and pagination. It is over 200 k-Gates. Specific to this design is the extensive use of both an FPGA and ASIC flow, for traditional synthesis as well as accelerated verification. Design Compiler, and SynplifyPro, Celaro andn Aptix platforms, co-simulation of Esterel source model with Denali memory models wre all exercised.
Design, simulation & synthesis of Memory Architectures including Cache
One of the early Esterel Studio designs, where an Esterel Studio model was used as the reference Executable Specification to define and validate the micro-architecture of a memory hierarchy for wireless applications. A public success story reports the productivity and clarity gained by using Esterel Studio.
An AXI Transactor for accelerated simulation on eVe ZeBu boards
Available as an Esterel Consortium project story, this application uses Esterel Studio to develop hardware / software transactors to raise system verification efficiency. The idea is to accelerate simulation of RTL blocks on FPGA boards. To do so, our customer needs efficient handling of communications between untimed software and cycle accurate hardware.This efficient interface is precisely the synthesizable transactors that can reach the 100 kHz range provided on eVe ZeBu boards.
NoC Generic Converter
This flexible and scalable Network on Chip (NoC) delivers significant advantages to system designers, including Quality of Service (QoS) support, and saving complex network topologies evaluations for each application. The NoC’s Network Interface allows any kind of IP protocol such as AXI, OCP, etc. to be converted into communication packets. The NoC includes a generic converter, that is a kind of bridge allowing data size conversion, communication retiming, and frequency conversion over two clock domains.
